1. Field of the Invention
The present invention generally relates to an improved method for fabricating MOS transistor gates and, more particularly, to a fabrication method for inverse-T type tungsten gate structures by reactive ion etch (RIE).
2. Description of the Prior Art
As will be appreciated by those skilled in the art, an inverse-T MOS transistor gate structure appears in cross section as an inverted "T". An article by Huang et al. entitled "A Novel Submicron LDD Transistor with Inverse-T Gate Structure," IEDM Tech Dig., 1986, pp. 742-745, which is herein incorporated by reference, discloses a typical lightly doped drain (LDD) transistor structure having an inverse-T gate structure made of polysilicon. In an inverse-T gate structure a portion of the gate extends beneath oxide sidewall spacers which surround and insulate the gate structure. Huang disclosed extending a portion of the gate beneath the oxide sidewall spacers improves transistor performance by providing better gate controllability.
Polysilicon inverse-T gates are widely used and are fabricated with methods well established in the art. Briefly, in these methods, a polysilicon film, from which the gate is to be formed, is deposited over a gate silicon oxide layer. The polysilicon is subjected to a reactive ion etch (RIE) which partially removes the polysilicon material adjacent a defined gate region. The etching process is stopped arbitrarily by timed etch so that a thin layer polysilicon of about 50-100 nanometers remains on the lower portion of the gate. Source and drain doping is accomplished by ion implantation directly through the thin polysilicon portion. Sidewall spacers, which act as a mask for additional source and drain implantation and etching steps, are formed around the gate by chemical vapor deposition (CVD). After the RIE and ion implantation steps the gate oxide layer is damaged. Therefore, it is necessary regrow the gate oxide layer to repair it. An additional problem with this approach is that the thickness of the remaining polysilicon is dependent on the etch process control.
Technology has steadily been moving to smaller transistor devices having superior performance characteristics. Polysilicon is the most commonly used material to fabricate MOS gate structures. Unfortunately, polysilicon possesses inherent material limitations which makes it unsuitable for submicron VLSI gate electrode applications. The resistances of polysilicon and silicided polysilicon gates are relatively high at 60 .OMEGA./square and 20 .OMEGA./square, respectively. The resistances of these gates become even higher as size is scaled down. In addition, it is difficult for buried channel MOSFETs to suppress their short channel effects when a polysilicon gate is used.
Naoki Kasai et al., Deep-Submicron Tungsten Gate CMOS Technology, IEDM Tech. Dig., 1988, discusses metal gate technology and, more particularly, focuses on the advantages of tungsten in VLSI gate electrode applications. Tungsten gates possess a resistance of less than 5 .OMEGA./square. Devices having tungsten gates have a 30% transconductance increase and have a low sub-threshold slope value which is responsible for a large on/off ratio.
In addition, tungsten is an ideal metal for CMOS transistor gates because it's work function is coincidentally near silicon's mid-bandgaps. This provides symmetrical operation for n- and p-channel devices with equal threshold values. See C. Y. Ting et al., Gate Materials Consideration for Submicron CMOS, Applied Surface Science, 38 (1989) pp. 416-428.
Although tungsten seems an ideal material for MOS gate electrodes, it is not without it's problems. Due to radical differences between tungsten and silicon processing requirements, no process exists which easily allows tungsten gates to be fabricated together with silicon MOS transistors. The most serious problem with tungsten is it forms volatile oxide at low temperature. As mentioned above, during the transistor fabrication process inherent damage occurs to the gate silicon oxide layer which necessitates regrowth. This is typically accomplished by oxidizing the silicon at temperatures of 900.degree.-1000.degree. C. in oxygen ambient for a period of time. Since, tungsten forms volatile oxides at only 300.degree. C., it is clear that a serious conflict exists.
To overcome this problem, N. Kobayashi et al., Highly Reliable Tungsten Gate Technology, Materials Research Society, 1987, proposes a wet hydrogen oxidation method wherein he suggests that he is able to oxidize the silicon without oxidizing the tungsten. The method involves using hydrogen with the appropriate amount of water along with a thin film if polysilicon, sandwiched between a tungsten gate and a gate oxide layer. This process is complicated and still requires polysilicon as an adhesive layer between the tungsten and the silicon oxide.